1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor (“TFT”), and more particularly, to a method of manufacturing a bottom gate TFT in which a polycrystalline channel region having a large grain size can be formed relatively simply and easily.
2. Description of the Related Art
Active research on a low temperature poly-Si (“LTPS”) TFT, which is used in light sources of organic light emitting display (“OLED”) devices or liquid crystal display (“LCD”) devices, has been conducted recently. Accordingly, research on a system on glass (“SOG”), in which an outer driver integrated circuit (“IC”) is never employed, has been further conducted. The outer driver IC is integrally formed on a display panel, and thus a connection line between the display panel and the outer driver IC is not required. Accordingly, display devices have a reduced error rate and improved reliability. Therefore an objective of this research includes development of a LTPS TFT for a SOG in which all display systems, including data and gate driver ICs, and a controller, are integrally formed on the display panel. To achieve this objective, the LTPS should have mobility greater than 400 cm2/Vsec and excellent uniformity. To date, a LTPS having these properties can not be manufactured using excimer laser annealing (“ELA”), sequential lateral solidification (“SLS”), metal-induced lateral crystallization (“MILC”), or the like, which are known to those of ordinary skill in the art.
Polycrystalline silicon is manufactured using various methods. For example, a method of directly depositing polycrystalline silicon and a method of crystallizing amorphous silicon after depositing the amorphous silicon can be used. Polycrystalline silicon manufactured by crystallizing has a large grain size. Thus the field effect mobility of the polycrystalline silicon is further increased, but the grain size uniformity of the polycrystalline silicon is further reduced. Conventional ELA can only enlarge the grain size of the polycrystalline silicon by a limited amount. To overcome this limit, Kim et al. (Kim et al., IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 6, June 2002, pgs. 315-317) suggests a method of manufacturing polycrystalline silicon having a grain size of several μm. A lateral grain having a length of 4.6 μm can be manufactured using a novel method of crystallizing. In this method, it is required that an oxide capping layer and an air gap be formed on upper and lower parts of amorphous silicon for controlling crystallization velocity. Accordingly, this method includes an additional operation. In particular, the air gap is formed by forming and removing an additional scarification layer, and the oxide capping layer is removed in a final step. The additional operation is not desirable in view of mass production, and in particular, may affect product yield, thus resulting in increased manufacturing costs.